C32025 digital signal processor megafunction cast, inc. may 2004 page 1 general description the C32025 is a 16-bit fixed-point digital signal processor core. it combines the flexibility of a high-speed controller with the numerical capability of an array processor. the C32025 has the same instruction set as the tms320c25 and also provides the same interrupts, serial interface and timer. developed for easy reuse with asics or fpgas, the core requires under 18000 asic gates. applications ? digital sound processing (adaptive filtering, fft, other special sound effects) ? voice recognition ? telecommunications (modems, codecs) ? medical equipment (diagnostics tools) ? computers peripherals ? various embedded data-intensive systems symbol
C32025 megafunction datasheet cast, inc. page 2 features ? control unit o 16-bit instruction decoding o repeat instructions for efficient use of program space and enhanced execution ? central arithmetic-logic unit o 16-bit parallel shifter; 32-bit arithmetic and logical operations o 16 x 16 bit parallel multiplier with a 32-bit product o 32-bit accumulator with output shifter o single-cycle multiply-and- accumulate instructions ? auxiliary registers o 8 16-bit registers for indirect addressing or temporary data storage o 16-bit auxiliary register arithmetic unit including operations with reversed-carry propagation ? memory addressing modes o direct - using a 9-bit page pointer and instruction word?s lowest 7-bits o indirect ? using the auxiliary register file o immediate ? less than 16-bit via instruction word or full 16-bit long immediate following the instruction word o block moves for data/program management ? 8-level hardware stack ? interrupt controller: 6 interrupt sources, excluding reset and a software interrupt ? synchronous serial port for direct codec interface ? 16-bit reload timer ? program memory organization o 4k-words of internal rom o internal 256-word ram block configurable either as program or data space o 64k-word external program space ? data memory organization o 2 internal 256-word and one 32- word ram blocks o 64k-words of external data space o 6 memory mapped registers ? 16 input and 16 output channels ? wait states for interfacing slower off-chip devices ? multiprocessing support o global data memory interface o synchronization input for synchronous multiprocessor configurations ? concurrent dma using an extended hold operation ? design is strictly synchronous with positive- edge clocking and synchronous reset, no internal tri-states.
C32025 megafunction datasheet cast, inc. may 2004 page 3 pin description name type polarity/ bus size description clk i rise master clock input all internal synchronous circuits clock clkout1 o - master clock output (fclk/4) when high it indicates intern al quarter-phases q3 and q4 clkout2 o - second clock output (fclk/4) when high it indicates intern al quarter-phases q2 and q3 rs_n i low hardware reset input active for 2 cycles resets the device mpmc i - microprocessor/microcomputer mode when low the internal rom is mapped into program space sync_n i fall synchronization input forces the internal quarter-phase to q1 hold_n i low hold input forces processor to place the data & address buses and control lines in the hi-z state holda_n o low hold acknowledge output indicates that processor is in the hold mode int0_n int1_n int2_n i i i low/fall low/fall low/fall external interrupt input s external interrupt 0 external interrupt 1 external interrupt 2 iack_n i low interrupt acknowledge indicates branching to the interrupt vector ps_o ds_o is_o o o o low low low program, data and i/o space select signals ps_tri ds_tri is_tri o o o high high high select signals tri-state control enables external tri-state buffers rw_o o - read/write output signal indicates external transfer direction. high means reading rw_tri o h read/write tri-state control enables external tri-state buffer strb_o o low strobe signa l low indicates an external bus cycle strb_tri o high strobe tri-state control signal enables external tri-state buffer ready i high data ready input indicates that external device is prepared for transfer to be completed bio_n i low branch control inpu t when active the bioz branch occurs br_n o low bus request output asserted when the processor requires access to external global data memory space
C32025 megafunction datasheet cast, inc. page 4 name type polarity/ bus size description msc_n o low microstate complete output indicates a completion of a memory operation xf o - external flag output general purpose output pin clkr i fall receive clock input clkx i rise transmit clock input dr i - serial data receive input data clocked by clkr dx_o o - serial data transmit output dx_tri o high serial transmit tri-state control active only while transmitting fsr i fall frame synchronization pulse for receive input fsx_i i fall frame synchronization pulse for transmit input fsx_o o fall frame synchronization pulse for transmit output fsx_tri o high frame synchronization pulse for transmit tri-state control extaddr_o extaddr_tri extdata_i extdata_o extdata_tri o o i o o 16 high 16 16 high external program/ data/ io interface address bus output address tri-state control data bus input data bus output data bus tri-state control romdata romaddr i o 16 12 internal program memory interface data input address output ram0data_i ram0data_o ram0addr ram0we ram0oe i o o o o 16 16 8 high high internal ram 0 interface data bus input data bus output data file address data file write enable data file output enable ram1data_i ram1data_o ram1addr ram1we ram1oe i o o o o 16 16 8 high high internal ram 1 interface data bus input data bus output data file address data file write enable data file output enable ram2data_i ram2data_o ram2addr ram2we ram2oe i o o o o 16 16 5 high high internal ram 2 interface data bus input data bus output data file address data file write enable data file output enable
C32025 megafunction datasheet cast, inc. page 5 block diagram phase generator reset control control unit interrupt controller peripherals auxiliary registers unit central arithmetic logic unit stack unit clk rs_n sync_n clkout1 clkout2 u_phasegenerator extaddr_o extdata_o extdata_i extdata_tri rw_o strb_o ds_o ps_o is_o ready ram0addr ram0data_o ram0data_i ram0oe ram0we ram1addr ram1data_o ram1data_i ram1oe ram1we ram2addr ram2data_o ram2data_i ram2oe ram2we romaddr romdata u_memdrivers extaddr_tri rw_tri strb_tri ds_tri ps_tri is_tri xf_o hold_n holda_n bio_n mpmc msc_n u_control u_irqdrivers br_n int2_n int1_n int0_n iack_n clkx dx_o dx_tri fsx_i fsx_o fsx_tri clkr dr fsr q1 q2 q3 q4 rst external bus interface block 0 interface block 1 interface block 2 interface internal rom interface pc_reg pfc_reg qir_reg ir_reg rptc_reg mcs_reg dp_reg fsm control unit st1_hm st1_xf external interrupts serial port transmitter serial port receiver timer tim_reg prd_reg drr_reg rsr_reg dxr_reg xsr_reg st0_intm st1_fo st1_txm st1_fsm imr_reg ifr_reg greg_reg u_auxreg ar0_reg ar1_reg ar2_reg ar3_reg ar4_reg ar5_reg ar6_reg ar7_reg st0_arp st1_arb arau u_calu acch_reg accl_reg st1_sxm st1_c st1_tc st0_ov st0_ovm st1_pm tr_reg pr_reg alu multiplier shifters u_stack hardware stack progaddr progbus dataaddr databus ( u_datamux ) instructions st1_cnf memory control unit C32025 block diagram
C32025 megafunction datasheet cast, inc. page 6 functional description the C32025 core is partitioned into modules as described below. control unit control unit consists of program count er (pc) and prefetch counter (pfc) used for program addressing and pipelining. sequencer is responsible fo r data flow organization. repeat coun ter (rptc) is used to repeat the execution of several instructions, especially data-intensive ones. memory control unit it is an interface between the processor and all on-chip or off-chip memories. there are three internal ram blocks interfaces, internal rom interface and external address and data buses. external wait states are possible. central arithmetic logic unit central arithmetic-logic unit. (calu) performs: ? sign-extended shifting ? 32-bit arithmetic operations ? 32-bit logic operations ? 16-bit signed or unsigned multiplication auxiliary registers unit eight auxiliary registers are used for indirect data addr essing or temporary data st orage. auxiliary registers arithmetic unit performs operations on current auxiliary register after each indirect data memory read/write. stack unit eight level hardware stack for pc storage during subroutine calls and interrupt service. peripherals there is one 16-bit continuously operating timer with programmable period. synchronous full-duplex serial interface can be used for interfacing serial ad/da converters and codecs. interrupt controller there are three external interrupts, both edge and leve l triggered. internal interrupt is generated at timer underflow or serial port transmit/receive completion. those six interrupts are maskable using interrupt mask register (imr). there is also one non-maskable software interrupt.
C32025 megafunction datasheet cast, inc. page 7 phase generator internal clock cycle divider. machine cycle consists of four main clock cycles. reset control reset input is sampled once a machine cy cle and distributed all over the core. device utilization & performance supported device utilization performance family tested les memory dsp f max flex2 epf10k100e-1 4532 m4ks; 1 m512 1 24 mhz acex2 ep1k100e-1 4532 m4ks; 1 m512 1 26 mhz apex1 ep20k200e-1 4420 19 esbs - 37 mhz apex21 ep2a15-7 4528 19 esbs - 65 mhz cyclone1 ep1c6-6 4066 37 esbs - 95 mhz stratix1 ep1s10-5 4370 7 eabs - 101 mhz startix21 ep2s15-3 3835 7 eabs - 130 mhz notes: 1. implemented with 544x16 bi t ram and 4096 x 16 bit rom 2. implemented with 544x16 bi t ram and 1048 x 16 bit rom core assumptions the iack_n and msc_n lines are valid only during the quarter-phases q1 and q2 (when clkout1 = 0). in other cases their behaviour is unpredictable in the original texas instruments tms320c25 device. the C32025 sets them to 1s in q3 and q4, except in the hold mode when msc_n remains 0. the original texas instruments tms320c25 serial port doesn't re-start properly when a frame sync pulse occurs in the middle of a transmission. the new transfer following a re-start is interrupted in a moment when previous transmission should be completed as if and there were no frame sync pulses, but the transferred data is re-loaded. the C32025 serial interface works properly as it is described in the specification document. the clkr and clkx inputs are clock inputs in the original texas instruments tms320c25 serial port registers. in C32025 they are not clock signals but are synchronously sampled at every positive edge of the main clock signal. the same applies to the external interrupts inputs int0_n, int1_n and int2_n. they are connected to a negative edge flip-flop in the original device, but in C32025 they are sampled synchronously with main clock signal. these changes cause delays in the serial port operation and forces the minimum length of an external interrupt pulse to at least one oscillator cycle. some registers are not reset by rs_n in the original texas instruments tms320c25 device, but are reset in the C32025. they are: acc 00000000h pr 00000000h tr 0000h arp 000 arb 000 dp 000000000 imr 000000 drr 0000h dxr 0000h stack all levels are reset to 0000h ovm 0 tc 0 ar0-ar7 all registers are reset to 0000h
C32025 megafunction datasheet cast, inc. page 8 verification methods the C32025 core?s functionality was verified by means of a proprietary hardware modeler. the same stimulus was applied to a hardware model that contained th e original texas instruments tms320c25 chip, and the results compared with the core?s simulation outputs. development environment ? vhdl source code for the C32025 ? synthesis support - complete set of synthesis scripts for synopsys ? simulation support ? a set of scripts an d macros for synopsys, mti, and aldec ? example chip_C32025 ? tms320c25 compatible design this design uses the C32025 and illustrates how to build and connect memories and tri-state buffers ? extensive hdl test bench that instantiates: o example design chip_C32025 o external ram o external rom o external i/o o clock generator o process that compares your simulation results with the expected results ? a collection of test assembler programs whic h are executed directly by the test bench ? a set of expected results ? additional documentation o architectural overview o hardware description o user guide o design support including consulting
C32025 megafunction datasheet cast, inc. page 9 deliverables netlist licenses ? post-synthesis edif netlist ? testbench (self-checking) ? vectors for testbenches ? expected results ? place & route script ? simulation script ? constraint file ? instantiation templates ? user documentation hdl source licenses ? synthesizable vhdl or verilog rtl source code ? testbench (self-checking) ? vectors for testbenches ? expected results ? simulation script ? synthesis script ? user documentation related information texas instruments url: http://www.ti.com contact information cast, inc. 11 stonewall court woodcliff lake, new jersey 07677 usa phone: +1 201-391-8300 fax: +1 201-391-8694 e-mail: info@cast-inc.com url: www.cast-inc.com this megafunction developed by the processor experts at evatronix sa copyright ? cast, inc. 2004. all rights reserved. contents subj ect to change without notice.
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